This invention relates to memory devices. More particularly, this invention relates to reducing digit equilibrate current during self-refresh mode in memory devices.
A memory device stores data in the form of binary digits. Memory can be arranged in an array containing rows and columns of memory cells, where each cell contains one bit of data (i.e., binary xe2x80x9c1xe2x80x9d or binary xe2x80x9c0xe2x80x9d). Memory is typically broadly classified as volatile and nonvolatile.
Nonvolatile memory retains its contents after power is turned off. Nonvolatile memory includes, for example, read only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), and flash memory.
Volatile memory, on the other hand, provides temporary data storage. Some types of volatile memory retain their content as long as power is on. Other types of volatile memory retain their content as long as power is on and refreshing techniques are applied. Volatile memory includes most types of random access memory (RAM) (e.g., static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM)) and non-random access memory (e.g., first-in first-out (FIFO), last-in first-out (LIFO), shift registers, and contents-addressable memory (CAM)). Volatile memory is ubiquitous in electronic systems such as computers.
In volatile memory such as RAM, a binary digit is stored either in a circuit element such as a flip-flop or as a charge on a capacitor. In particular, SDRAMs store data as charge on a capacitor. The voltage level across the capacitor represents the binary digit. For example, a voltage of about VDD (i.e., source voltage) represents a binary xe2x80x9c1xe2x80x9d while a voltage of about 0 volts (i.e., ground) represents a binary xe2x80x9c0.xe2x80x9d Over time, the capacitor discharges, causing the voltage across the capacitor to change. In some instances, a defect in the capacitor can also cause the voltage to change. If the memory cell is not refreshed, incorrect data may be represented in the memory cell.
In order to preserve a memory cell""s contents, the memory cell must be refreshed periodically. During this refresh period, a sense amplifier detects and amplifies (i.e., restores) the voltage level in the memory cell. For example, when a voltage representing a binary xe2x80x9c1xe2x80x9d stored in a memory cell loses charge so that the voltage across the capacitor becomes less than VDD, the sense amplifier will amplify that voltage back to VDD. When a voltage representing a binary xe2x80x9c0xe2x80x9d stored in a memory cell is increased, for example, because of a defect in the capacitor, the sense amplifier will restore that voltage back to ground.
For SDRAM, there are generally two automated memory refresh methods: an auto-refresh mode and a self-refresh mode. Auto-refresh mode is typically used during normal operation (e.g., when an electronic system is in a mode other than low power or sleep mode). It begins when the system issues an auto-refresh command, which the system does periodically. Each auto-refresh command executes a self-timed, precharge-to-active sequence on one or more rows corresponding to an internally-generated address in memory. In self-refresh mode, auto-refresh commands are internally triggered by an on-chip interval timer. Self-refresh mode is typically used when the is system is in low-power or sleep mode, which is initiated by a clock enable signal that typically switches from high to low (i.e., from binary xe2x80x9c1xe2x80x9d to binary xe2x80x9c0xe2x80x9d) immediately followed by an auto-refresh command.
Memory is typically divided into sub-arrays (i.e., sections) with row lines associated with each row of memory cells in each sub-array and with digit pairs (i.e., complementary digit lines) associated with each column of memory cells in each sub-array. A given sub-array typically spans a contiguous digit line and row line bus. Generally, one sub-array is refreshed at a time. While a given sub-array is idle during self-refresh mode, digit pairs are continuously precharged. When digit pairs are precharged, the lines are forced to a median voltage between the source voltage and ground (e.g., VDD/2). A digit equilibrate generator can be used, for example, to generate this median voltage. A conductive path is formed from the digit equilibrate generator to the digit pairs when a bleeder device is enabled.
Much engineering goes into optimizing a bleeder device to supply sufficient current to handle normal leakage mechanisms on the digit pairs while at the same time limiting the bleeder device from supplying too much current when there is a significant defect that shorts a row line to a digit line. These defects cause additional power consumption when the bleeder device is enabled since the row line is grounded and the digits are precharged to the median voltage. This optimization is often accomplished by designing the bleeder device with a higher resistance. However, this typically increases the area of the bleeder device, which is undesirable in light of the trend towards smaller memory devices with increased memory capacity.
In view of the foregoing, it would be desirable to provide a self-refresh mode that pulses a bleeder device to reduce the digit equilibrate current without increasing the area of the bleeder device.
It is an object of this invention to provide a self-refresh mode that pulses a bleeder device to reduce the digit equilibrate current without increasing the area of the bleeder device.
In accordance with this invention, apparatus and methods for reducing digit equilibrate current during self-refresh mode are provided that reduce the time that digit pairs associated with a column of memory cells in each sub-array are precharged with the bleeder device enabled and that provides a substantially consistent precharge-to-active versus active-to-precharge duty cycle for all internally generated refresh cycles across all sub-arrays. A duty cycle represents a proportion of time that a system is in a particular cycle (e.g., in a precharge cycle, in an active cycle).
In self-refresh mode, each sub-array can refresh a row of memory cells before another row of memory cells in a given sub-array is refreshed. An internal auto-refresh counter and a row address block is used to select the sub-array and a row of memory cells to refresh within that sub-array. Refreshing a row of memory cells in a sub-array has two cycles: a precharge cycle and an active cycle (A). The precharge cycle (P) can further be divided into two sub-cycles: a bleeder enable cycle (BE) and a bleeder disable cycle (BD). In a is bleeder enable cycle, a bleeder driver associated with a selected sub-array enables all bleeder gates in the selected sub-array to drive their digit pairs to a precharge voltage generated by a digit equilibrate generator. The digit equilibrate generator generates an intermediate voltage between the source voltage and ground (e.g., VDD/2, where VDD is the source voltage). In another embodiment, each pair of sub-arrays shares a common bleeder driver that is continuously enabled. Isolation transistors are pulsed to allow the digit pairs in the selected sub-array to be precharged. In an active cycle, the selected row line in the selected sub-array is activated (e.g., set to binary xe2x80x9c1xe2x80x9d), and the corresponding row of memory cells are refreshed.